用于雷达的高集成d波段多通道收发芯片

V. Issakov, Andrea Bilato, Vera Kurz, D. Englisch, A. Geiselbrechtinger
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引用次数: 17

摘要

本文提出了一种采用0.13 μ m SiGe BiCMOS技术实现的低功耗、高集成度d波段收发器芯片。集成级别包括三个接收(RX)通道,一个发送(TX)通道,本地振荡器(LO)信号产生和分配网络,分频器和用于数字可重构的串行外设接口(SPI)。在118 GHz时,接收机的峰值增益为14 dB,而在118 GHz时,发射机的输出功率为- 6 dBm。压控振荡器采用推推式Colpitts拓扑结构实现。此外,它的输出用倍频器乘以2。因此,发射机输出信号在117 - 126 GHz的频率范围内连续可调,同时在120 GHz的1mhz偏移处实现- 93.5 dBc /Hz的相位噪声测量。整个收发器从单个1.8 V电源吸取195 mA。单个RX通道消耗19 mA,而单个TX消耗25 mA。包含焊盘的电路占用的芯片面积仅为3.5 mm × 2.75 mm,仅受通道之间隔离所需的分离的限制。该收发器提供了具有竞争力的性能,适用于120 GHz左右的连续波雷达应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Highly Integrated D-Band Multi-Channel Transceiver Chip for Radar Applications
This paper presents a low-power, highly-integrated D-Band transceiver chip realized in a 0.13 µm SiGe BiCMOS technology. The integration level includes three receiver (RX) channels, one transmitter (TX) channel, local oscillator (LO) signal generation and distribution network, frequency dividers and serial peripheral interface (SPI) for digital reconfigurability. The receiver achieves a peak gain of 14 dB at 118 GHz, while the transmitter achieves an output power of −6 dBm at 118 GHz. The VCO is realized in a push-push Colpitts topology. Additionally, its output is multiplied by two using a frequency doubler. Hence the transmitter output signal is continuously tunable in the frequency range 117 − 126 GHz, while achieving a measured phase noise of − 93.5 dBc /Hz at 1 MHz offset at 120 GHz. The entire transceiver draws 195 mA from a single 1.8 V supply. A single RX channel draws 19 mA, while a single TX consumes 25 mA. The circuit including pads occupies a chip area of only 3.5 mm × 2.75 mm, which is limited only by the separation necessary for isolation between the channels. The transceiver provides a competitive performance and is suitable for continuous-wave radar applications around 120 GHz.
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