面向下一代体FinFET和GAA NW技术节点的最佳ESD二极管

2017 IEEE International Electron Devices Meeting (IEDM) Pub Date : 2017-12-01 DOI:10.1109/IEDM.2017.8268346

S.-H. Chen, G. Hellings, D. Linten, T. Chiarella, H. Mertens, R. Boschke, J. Mitard, S. Kubicek, R. Ritzenthaler, E. Bury, N. Wang, G. Groeseneken, A. Mocuta, N. Horiguchi

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引用次数: 9

摘要

除了尺寸缩放之外，CMOS路线图中的新工艺选项通常会导致ESD器件性能的降低。利用3D TCAD和ESD表征，探讨了器件架构、线中线接触方案和S/D外延工艺选项对下一代批量FF和GAA技术中ESD二极管性能的影响。

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Towards optimal ESD diodes in next generation bulk FinFET and GAA NW technology nodes

Beyond dimensional scaling, new process options in CMOS roadmap often result in degradation of ESD device performance. Using 3D TCAD and ESD characterization, the impacts of device architecture, middle-of-line contact scheme, and S/D epitaxy process options are explored on ESD diode performance in next generation bulk FF and GAA technologies.

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2017 IEEE International Electron Devices Meeting (IEDM)

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