{"title":"流水线处理器的行为设计和测试辅助","authors":"H. Iwashita, T. Nakata, F. Hirose","doi":"10.1109/ATS.1992.224427","DOIUrl":null,"url":null,"abstract":"The authors propose a new concept in designing and testing processors. This approach generates behavioral-level test environments in VHDL for specific processor mechanisms, including automatic generations of test programs and behavioral descriptions. The authors have implemented an application to pipeline controllers.<<ETX>>","PeriodicalId":208029,"journal":{"name":"Proceedings First Asian Test Symposium (ATS `92)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Behavioral design and test assistance for pipelined processors\",\"authors\":\"H. Iwashita, T. Nakata, F. Hirose\",\"doi\":\"10.1109/ATS.1992.224427\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors propose a new concept in designing and testing processors. This approach generates behavioral-level test environments in VHDL for specific processor mechanisms, including automatic generations of test programs and behavioral descriptions. The authors have implemented an application to pipeline controllers.<<ETX>>\",\"PeriodicalId\":208029,\"journal\":{\"name\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"volume\":\"56 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-11-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings First Asian Test Symposium (ATS `92)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1992.224427\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings First Asian Test Symposium (ATS `92)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1992.224427","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Behavioral design and test assistance for pipelined processors
The authors propose a new concept in designing and testing processors. This approach generates behavioral-level test environments in VHDL for specific processor mechanisms, including automatic generations of test programs and behavioral descriptions. The authors have implemented an application to pipeline controllers.<>
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