{"title":"双差分记录和AGC使用放大器ASIC","authors":"Shin-Liang Deng, Chun-Yi Li, R. Rieger","doi":"10.1109/SOCC.2011.6085121","DOIUrl":null,"url":null,"abstract":"An automatic gain control circuit (AGC) and a circuit for double-differential (DD) recording are implemented using an integrated variable gain circuit. The integrated circuit enables gain trimming by variation of the chip clock timing. A microcontroller is used to provide the clocks. AGC and DD setups with a simple 2-chip and 3-chip system respectively are realized. Measured results confirm a gain tuning range of 22.7 dB and interference suppression of 41.4 dB in the balanced DD arrangement, and power consumption of 318 µW.","PeriodicalId":365422,"journal":{"name":"2011 IEEE International SOC Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Double-differential recording and AGC using amplifier ASIC\",\"authors\":\"Shin-Liang Deng, Chun-Yi Li, R. Rieger\",\"doi\":\"10.1109/SOCC.2011.6085121\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An automatic gain control circuit (AGC) and a circuit for double-differential (DD) recording are implemented using an integrated variable gain circuit. The integrated circuit enables gain trimming by variation of the chip clock timing. A microcontroller is used to provide the clocks. AGC and DD setups with a simple 2-chip and 3-chip system respectively are realized. Measured results confirm a gain tuning range of 22.7 dB and interference suppression of 41.4 dB in the balanced DD arrangement, and power consumption of 318 µW.\",\"PeriodicalId\":365422,\"journal\":{\"name\":\"2011 IEEE International SOC Conference\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-11-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2011 IEEE International SOC Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCC.2011.6085121\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE International SOC Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCC.2011.6085121","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Double-differential recording and AGC using amplifier ASIC
An automatic gain control circuit (AGC) and a circuit for double-differential (DD) recording are implemented using an integrated variable gain circuit. The integrated circuit enables gain trimming by variation of the chip clock timing. A microcontroller is used to provide the clocks. AGC and DD setups with a simple 2-chip and 3-chip system respectively are realized. Measured results confirm a gain tuning range of 22.7 dB and interference suppression of 41.4 dB in the balanced DD arrangement, and power consumption of 318 µW.
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