基于CCII+电流输送的BIC监视器,用于复杂CMOS电路的I/sub DDQ/测试

V. Stopjaková, H. Manhaeve
{"title":"基于CCII+电流输送的BIC监视器,用于复杂CMOS电路的I/sub DDQ/测试","authors":"V. Stopjaková, H. Manhaeve","doi":"10.1109/EDTC.1997.582369","DOIUrl":null,"url":null,"abstract":"In this paper, a quiescent built-in current (BIC) monitor based on a second generation current conveyor CCII+ is presented. The monitor circuit minimises the power supply voltage degradation and provides a sensitive detection of defects that cause an elevated value of the I/sub DDQ/ current The proposed monitor offers an accurate current measurement and has a wide operation range. The CCII+ based current monitor is able to handle huge digital ASICs. Significant results summarising possibilities and limitations of the circuit are discussed as well. The design was implemented through Alcatel-Mietec 0.7 /spl mu/m CMOS technology and an evaluation of the prototype chips has been carried out. An experimental application of the proposed monitor in new analogue self-test structure was considered.","PeriodicalId":297301,"journal":{"name":"Proceedings European Design and Test Conference. ED & TC 97","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":"{\"title\":\"CCII+ current conveyor based BIC monitor for I/sub DDQ/ testing of complex CMOS circuits\",\"authors\":\"V. Stopjaková, H. Manhaeve\",\"doi\":\"10.1109/EDTC.1997.582369\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a quiescent built-in current (BIC) monitor based on a second generation current conveyor CCII+ is presented. The monitor circuit minimises the power supply voltage degradation and provides a sensitive detection of defects that cause an elevated value of the I/sub DDQ/ current The proposed monitor offers an accurate current measurement and has a wide operation range. The CCII+ based current monitor is able to handle huge digital ASICs. Significant results summarising possibilities and limitations of the circuit are discussed as well. The design was implemented through Alcatel-Mietec 0.7 /spl mu/m CMOS technology and an evaluation of the prototype chips has been carried out. An experimental application of the proposed monitor in new analogue self-test structure was considered.\",\"PeriodicalId\":297301,\"journal\":{\"name\":\"Proceedings European Design and Test Conference. ED & TC 97\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-03-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"24\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings European Design and Test Conference. ED & TC 97\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDTC.1997.582369\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings European Design and Test Conference. ED & TC 97","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTC.1997.582369","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 24

摘要

本文介绍了一种基于第二代电流输送器CCII+的静态内置电流监测仪。监测电路最大限度地减少了电源电压下降,并提供了一个敏感的缺陷检测,导致I/sub DDQ/电流升高的值。建议的监测提供了一个准确的电流测量,并具有广泛的工作范围。基于CCII+的电流监视器能够处理巨大的数字asic。讨论了总结电路的可能性和局限性的重要结果。该设计通过Alcatel-Mietec 0.7 /spl μ m CMOS技术实现,并对原型芯片进行了评估。考虑了该监测器在新型模拟自检结构中的实验应用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
CCII+ current conveyor based BIC monitor for I/sub DDQ/ testing of complex CMOS circuits
In this paper, a quiescent built-in current (BIC) monitor based on a second generation current conveyor CCII+ is presented. The monitor circuit minimises the power supply voltage degradation and provides a sensitive detection of defects that cause an elevated value of the I/sub DDQ/ current The proposed monitor offers an accurate current measurement and has a wide operation range. The CCII+ based current monitor is able to handle huge digital ASICs. Significant results summarising possibilities and limitations of the circuit are discussed as well. The design was implemented through Alcatel-Mietec 0.7 /spl mu/m CMOS technology and an evaluation of the prototype chips has been carried out. An experimental application of the proposed monitor in new analogue self-test structure was considered.
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