Alphabet based selected character decoding for area efficient pattern matching architecture on FPGAs

In this paper, we present an idea of selected character decoding (SCD) based on alphabet for network usage, especially network intrusion detection system (NIDS). SCD extends the approaches using decoder in order to achieve the least number of comparison units. The definitions of alphabet help to give the selections of characters for decoding, especially the alphabets of vertical left alignment (Avla). This paper also introduces a pattern matching architecture with alphabet based SCD. This architecture takes full advantages of the idea of pre-decoding and achieves the same high frequency as the one based on decoder while saving more than half resources. The third contribution of this paper is the idea and initial model for resource estimation just based on given pattern sets. To 1197 real patterns in Snort v2.3.3, experimental results show the resources used in alphabet based SCD is just 35.1% of the one in traditional 8-256 decoder. Targeting on Xilinx Virtex2Pro20 (speed grade 7), the pattern matching architecture can achieve 271 mHz, with 4.3Gbps throughput and can be scalable linearly.