{"title":"容错ALU系统","authors":"A. Majumdar, S. Nayyar, J. Sengar","doi":"10.1109/ICCS.2012.36","DOIUrl":null,"url":null,"abstract":"This paper presents the design of FAULT TOLERANT ALU SYSTEM by using Triple Modular Redundancy. ALU is a critical component of microprocessor and is the core component of central processing unit. Therefore, it is necessary for making the ALU to be fault tolerant. The use of voting logic and disagreement detector has been implied in making the ALU system to be fault tolerant. The source code for the following was developed in VerilogHDL. The software used was XilinxISE.","PeriodicalId":429916,"journal":{"name":"2012 International Conference on Computing Sciences","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-09-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"18","resultStr":"{\"title\":\"Fault Tolerant ALU System\",\"authors\":\"A. Majumdar, S. Nayyar, J. Sengar\",\"doi\":\"10.1109/ICCS.2012.36\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of FAULT TOLERANT ALU SYSTEM by using Triple Modular Redundancy. ALU is a critical component of microprocessor and is the core component of central processing unit. Therefore, it is necessary for making the ALU to be fault tolerant. The use of voting logic and disagreement detector has been implied in making the ALU system to be fault tolerant. The source code for the following was developed in VerilogHDL. The software used was XilinxISE.\",\"PeriodicalId\":429916,\"journal\":{\"name\":\"2012 International Conference on Computing Sciences\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-09-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"18\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2012 International Conference on Computing Sciences\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCS.2012.36\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2012 International Conference on Computing Sciences","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCS.2012.36","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This paper presents the design of FAULT TOLERANT ALU SYSTEM by using Triple Modular Redundancy. ALU is a critical component of microprocessor and is the core component of central processing unit. Therefore, it is necessary for making the ALU to be fault tolerant. The use of voting logic and disagreement detector has been implied in making the ALU system to be fault tolerant. The source code for the following was developed in VerilogHDL. The software used was XilinxISE.
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