{"title":"用WEE优化方法减少晶圆边缘缺陷","authors":"Taiki Murata, Masayuki Sato, T. Goto","doi":"10.1109/ISSM.2007.4446900","DOIUrl":null,"url":null,"abstract":"In this paper, A unique defect caused by inter layer dielectric (ILD) film peeling from wafer edge is reported. The root cause analysis by using wafer edge/bevel inspection tool revealed that the source of the ILD film peeling is residual photoresist at wafer edge. Wafer edge exposure (WEE) condition was optimized to suppress the resist residue and consequent film peeling from wafer edge.","PeriodicalId":325607,"journal":{"name":"2007 International Symposium on Semiconductor Manufacturing","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Reduction of wafer edge induced defect by WEE optimization\",\"authors\":\"Taiki Murata, Masayuki Sato, T. Goto\",\"doi\":\"10.1109/ISSM.2007.4446900\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, A unique defect caused by inter layer dielectric (ILD) film peeling from wafer edge is reported. The root cause analysis by using wafer edge/bevel inspection tool revealed that the source of the ILD film peeling is residual photoresist at wafer edge. Wafer edge exposure (WEE) condition was optimized to suppress the resist residue and consequent film peeling from wafer edge.\",\"PeriodicalId\":325607,\"journal\":{\"name\":\"2007 International Symposium on Semiconductor Manufacturing\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Symposium on Semiconductor Manufacturing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSM.2007.4446900\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Symposium on Semiconductor Manufacturing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSM.2007.4446900","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Reduction of wafer edge induced defect by WEE optimization
In this paper, A unique defect caused by inter layer dielectric (ILD) film peeling from wafer edge is reported. The root cause analysis by using wafer edge/bevel inspection tool revealed that the source of the ILD film peeling is residual photoresist at wafer edge. Wafer edge exposure (WEE) condition was optimized to suppress the resist residue and consequent film peeling from wafer edge.