{"title":"用于384×288 IRFPA ROIC的列并联14b SAR adc的低功耗自动归零比较器","authors":"Meng Chen, Wengao Lu, Tingting Tao, Yacong Zhang, Zhongjian Chen","doi":"10.1109/EDSSC.2013.6628037","DOIUrl":null,"url":null,"abstract":"This paper presents a low power comparator with auto-zeroed technique for the readout chain of a 384×288 infrared focal plane array (IRFPA). To overcome the high power consumption of column-paralleled application, a novel inverter=based pre-amplifier is introduced. The performances of the proposed comparator are verified by a 14-bit column paralleled Successive-Approximation-Register (SAR) A/D converter which is developed in a 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 93dB at a sampling clock of 31.25 KHz with an input signal of 1.009 KHz. The overall static power of the 384 column-paralleled ADCs is less than 50mW.","PeriodicalId":333267,"journal":{"name":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-06-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A low-power auto-zeroed comparator for column-paralleled 14b SAR ADCs of 384×288 IRFPA ROIC\",\"authors\":\"Meng Chen, Wengao Lu, Tingting Tao, Yacong Zhang, Zhongjian Chen\",\"doi\":\"10.1109/EDSSC.2013.6628037\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a low power comparator with auto-zeroed technique for the readout chain of a 384×288 infrared focal plane array (IRFPA). To overcome the high power consumption of column-paralleled application, a novel inverter=based pre-amplifier is introduced. The performances of the proposed comparator are verified by a 14-bit column paralleled Successive-Approximation-Register (SAR) A/D converter which is developed in a 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 93dB at a sampling clock of 31.25 KHz with an input signal of 1.009 KHz. The overall static power of the 384 column-paralleled ADCs is less than 50mW.\",\"PeriodicalId\":333267,\"journal\":{\"name\":\"2013 IEEE International Conference of Electron Devices and Solid-state Circuits\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-06-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE International Conference of Electron Devices and Solid-state Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDSSC.2013.6628037\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE International Conference of Electron Devices and Solid-state Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDSSC.2013.6628037","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
本文介绍了一种用于384×288红外焦平面阵列(IRFPA)读出链的低功耗自动归零比较器。为了克服柱并联应用的高功耗问题,提出了一种新型的基于逆变器的前置放大器。采用基于0.35um cmos工艺技术开发的14位列并行逐次逼近寄存器(SAR) a /D转换器验证了该比较器的性能。在采样时钟为31.25 KHz,输入信号为1.009 KHz时,A/D转换器的SFDR高达93dB。384列并联adc的总静态功率小于50mW。
A low-power auto-zeroed comparator for column-paralleled 14b SAR ADCs of 384×288 IRFPA ROIC
This paper presents a low power comparator with auto-zeroed technique for the readout chain of a 384×288 infrared focal plane array (IRFPA). To overcome the high power consumption of column-paralleled application, a novel inverter=based pre-amplifier is introduced. The performances of the proposed comparator are verified by a 14-bit column paralleled Successive-Approximation-Register (SAR) A/D converter which is developed in a 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 93dB at a sampling clock of 31.25 KHz with an input signal of 1.009 KHz. The overall static power of the 384 column-paralleled ADCs is less than 50mW.