{"title":"高密度300ps BiCMOS GRA","authors":"J. Eckhardt, S. Chu, K. Umino","doi":"10.1109/BIPOL.1992.274056","DOIUrl":null,"url":null,"abstract":"A multiport BiCMOS embedded static RAM (SRAM) is introduced for use as a growable register array (GRA) in high-performance gate array technologies. This design provides read access times equivalent to those of bipolar RAMs, while maintaining soft-error rates that are lower than those of CMOS. Read access times of 300 ps were achieved by eliminating all emitter-coupled-logic (ECL) to CMOS conversion from the read paths. The current implementation allows array densities as high as 200 kb embedded in gate array logic.<<ETX>>","PeriodicalId":286222,"journal":{"name":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-10-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A high-density 300 ps BiCMOS GRA\",\"authors\":\"J. Eckhardt, S. Chu, K. Umino\",\"doi\":\"10.1109/BIPOL.1992.274056\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A multiport BiCMOS embedded static RAM (SRAM) is introduced for use as a growable register array (GRA) in high-performance gate array technologies. This design provides read access times equivalent to those of bipolar RAMs, while maintaining soft-error rates that are lower than those of CMOS. Read access times of 300 ps were achieved by eliminating all emitter-coupled-logic (ECL) to CMOS conversion from the read paths. The current implementation allows array densities as high as 200 kb embedded in gate array logic.<<ETX>>\",\"PeriodicalId\":286222,\"journal\":{\"name\":\"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-10-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.1992.274056\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.1992.274056","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A multiport BiCMOS embedded static RAM (SRAM) is introduced for use as a growable register array (GRA) in high-performance gate array technologies. This design provides read access times equivalent to those of bipolar RAMs, while maintaining soft-error rates that are lower than those of CMOS. Read access times of 300 ps were achieved by eliminating all emitter-coupled-logic (ECL) to CMOS conversion from the read paths. The current implementation allows array densities as high as 200 kb embedded in gate array logic.<>
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
