Ultra low-power 7T SRAM cell design based on CMOS

In his paper a 7T SRAM cell operating well in low voltages is presented. Suitable read operation structure is provided by controlling the drain induced barrier lowering (DIBL) effect and body-source voltage in the hold `1' state. The read-operation structure of the proposed cell utilizes the single transistor which leads to a larger write margin. The simulation results at 90nm TSMC CMOS demonstrate the outperforms of the proposed SRAM cell in terms of power dissipation, write margin, sensitivity to process variations as compared with the other most efficient low-voltage SRAM cells.