Robust high-speed low input impedance CMOS current comparator

In this paper, a robust high speed low input impedance CMOS current comparator is proposed. The circuit uses modified Wilson current-mirror to perform a current subtraction. Negative feedback is employed to reduce input impedances of the circuit. The diode connected transistors of the same type (NMOS) are used at the output making the circuit immune to the process variation. HSPICE is used to verify the circuit performance and the results show the propagation delay of 1.67 nsec with an average power dissipation of 0.63 mW using a standard 0.5 /spl mu/m CMOS technology for an input current of /spl plusmn/0.1 /spl mu/A at the supply voltage of 3 V. The input impedances of the proposed current comparator are 123 /spl Omega/ and 126 /spl Omega/ while the maximum output voltage variation is only 1.9%.