{"title":"用于容错架构的量子电路的设计与实现","authors":"Konstantinos Prousalis, Nikos Konofaos","doi":"10.1109/PACET.2017.8259984","DOIUrl":null,"url":null,"abstract":"The circuit model of quantum computation is the most common way to achieve a high-level representation of the computing evolution in a quantum computer. By using an already proposed software tool, the design and implementation processes are described for different architectures. The utility and potency of this tool is tested. Some representative examples are demonstrated to depict how it actually contributes to the implementation of a quantum circuit. Particular facilities may speedup the implementation process. A logic circuit's implementation can be automatically transformed into a fault-tolerant one by including the auxiliary encoding circuit overhead. Different design techniques are supported and recovery mechanisms can be included.","PeriodicalId":171095,"journal":{"name":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design and implementation of quantum circuits for fault-tolerant architectures\",\"authors\":\"Konstantinos Prousalis, Nikos Konofaos\",\"doi\":\"10.1109/PACET.2017.8259984\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The circuit model of quantum computation is the most common way to achieve a high-level representation of the computing evolution in a quantum computer. By using an already proposed software tool, the design and implementation processes are described for different architectures. The utility and potency of this tool is tested. Some representative examples are demonstrated to depict how it actually contributes to the implementation of a quantum circuit. Particular facilities may speedup the implementation process. A logic circuit's implementation can be automatically transformed into a fault-tolerant one by including the auxiliary encoding circuit overhead. Different design techniques are supported and recovery mechanisms can be included.\",\"PeriodicalId\":171095,\"journal\":{\"name\":\"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)\",\"volume\":\"9 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/PACET.2017.8259984\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Panhellenic Conference on Electronics and Telecommunications (PACET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/PACET.2017.8259984","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design and implementation of quantum circuits for fault-tolerant architectures
The circuit model of quantum computation is the most common way to achieve a high-level representation of the computing evolution in a quantum computer. By using an already proposed software tool, the design and implementation processes are described for different architectures. The utility and potency of this tool is tested. Some representative examples are demonstrated to depict how it actually contributes to the implementation of a quantum circuit. Particular facilities may speedup the implementation process. A logic circuit's implementation can be automatically transformed into a fault-tolerant one by including the auxiliary encoding circuit overhead. Different design techniques are supported and recovery mechanisms can be included.