{"title":"IIR SC多级分馏器的自动合成","authors":"Cheong Ngai, R. Martins","doi":"10.1109/MWSCAS.2004.1354350","DOIUrl":null,"url":null,"abstract":"This paper presents an automated system for the design of IIR SC multistage decimators. Through the integration of different existing programs it provides a user-friendly interface that allows the implementation of IIR SC decimators from the top filter specifications down to the circuit layout. It allows the automated design of a cascade of decimator stages in order to obtain a sufficiently high ratio between the sampling frequency and the maximum signal frequency of interest, and also simplifies the circuit through the minimization of the silicon area. Two design examples are given to demonstrate the feasibility of this approach.","PeriodicalId":185817,"journal":{"name":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","volume":"60 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-07-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Automatic synthesis of IIR SC multistage decimators\",\"authors\":\"Cheong Ngai, R. Martins\",\"doi\":\"10.1109/MWSCAS.2004.1354350\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents an automated system for the design of IIR SC multistage decimators. Through the integration of different existing programs it provides a user-friendly interface that allows the implementation of IIR SC decimators from the top filter specifications down to the circuit layout. It allows the automated design of a cascade of decimator stages in order to obtain a sufficiently high ratio between the sampling frequency and the maximum signal frequency of interest, and also simplifies the circuit through the minimization of the silicon area. Two design examples are given to demonstrate the feasibility of this approach.\",\"PeriodicalId\":185817,\"journal\":{\"name\":\"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.\",\"volume\":\"60 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-07-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSCAS.2004.1354350\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSCAS.2004.1354350","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Automatic synthesis of IIR SC multistage decimators
This paper presents an automated system for the design of IIR SC multistage decimators. Through the integration of different existing programs it provides a user-friendly interface that allows the implementation of IIR SC decimators from the top filter specifications down to the circuit layout. It allows the automated design of a cascade of decimator stages in order to obtain a sufficiently high ratio between the sampling frequency and the maximum signal frequency of interest, and also simplifies the circuit through the minimization of the silicon area. Two design examples are given to demonstrate the feasibility of this approach.
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