The effect of switch speed, and buffer limitations on the performance of a multichannel ATM switch with output queueing

The authors present a queuing analysis of an internally nonblocking N*N ATM (asynchronous transfer mode) switch employing multichannel transmission groups with partially shared output buffers. The analysis is based on a discrete-time D/sup (A)//D/c/B queuing model. Bulk input traffic with constant bulk interarrival time (D) and general bulk-size distribution (A) is considered. The impact of switch speedup on the performance is explicitly taken into account. It is found that the switch speedup required to approach the ideal performance, obtained by having the switch fabric run N times as fast as the input and output channels, is small compared with N. This makes the practical realization of the proposed switch architecture feasible.<>