{"title":"WASP示范项目:晶圆级系统的工程设计","authors":"I. Jalowiecki, S. Hedge","doi":"10.1109/ICWSI.1990.63881","DOIUrl":null,"url":null,"abstract":"The aim of the Brunel University/Aspex Microsystems WASP (WSI Associative String Processor) project is the production of high performance, cost-effective, practical monolithic Wafer-Scale Parallel Processing systems. The Associative String Processor (ASP) architecture is a massively parallel, fine-grain architecture, suitable for VLSI, ULSI and WSI fabrication. Following a considerable period of test chip experimentation, addressing fundamental WSI design issues, this work graduated to a programme of first technology, and then functional demonstrators. Designed to progress towards a practical WASP in a series of carefully planned steps, these devices prove the feasibility of the WASP architecture and provide engineering data and proof of principle unobtainable by any other means. The authors summarise the demonstrator programme to date, including the test results from the first technology demonstrator (WASP 1) and the architecture of the second technology demonstrator (WASP 2).<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"102 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"13","resultStr":"{\"title\":\"The WASP demonstrator programme: the engineering of a wafer-scale system\",\"authors\":\"I. Jalowiecki, S. Hedge\",\"doi\":\"10.1109/ICWSI.1990.63881\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The aim of the Brunel University/Aspex Microsystems WASP (WSI Associative String Processor) project is the production of high performance, cost-effective, practical monolithic Wafer-Scale Parallel Processing systems. The Associative String Processor (ASP) architecture is a massively parallel, fine-grain architecture, suitable for VLSI, ULSI and WSI fabrication. Following a considerable period of test chip experimentation, addressing fundamental WSI design issues, this work graduated to a programme of first technology, and then functional demonstrators. Designed to progress towards a practical WASP in a series of carefully planned steps, these devices prove the feasibility of the WASP architecture and provide engineering data and proof of principle unobtainable by any other means. The authors summarise the demonstrator programme to date, including the test results from the first technology demonstrator (WASP 1) and the architecture of the second technology demonstrator (WASP 2).<<ETX>>\",\"PeriodicalId\":206140,\"journal\":{\"name\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"volume\":\"102 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-01-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"13\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1990.63881\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 Proceedings. International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1990.63881","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The WASP demonstrator programme: the engineering of a wafer-scale system
The aim of the Brunel University/Aspex Microsystems WASP (WSI Associative String Processor) project is the production of high performance, cost-effective, practical monolithic Wafer-Scale Parallel Processing systems. The Associative String Processor (ASP) architecture is a massively parallel, fine-grain architecture, suitable for VLSI, ULSI and WSI fabrication. Following a considerable period of test chip experimentation, addressing fundamental WSI design issues, this work graduated to a programme of first technology, and then functional demonstrators. Designed to progress towards a practical WASP in a series of carefully planned steps, these devices prove the feasibility of the WASP architecture and provide engineering data and proof of principle unobtainable by any other means. The authors summarise the demonstrator programme to date, including the test results from the first technology demonstrator (WASP 1) and the architecture of the second technology demonstrator (WASP 2).<>
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