基于时复用数字差分放大的0.01mm2、0.4V-VDD、4.5 nw功率的直流耦合数字采集前端

ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC) Pub Date : 2022-09-19 DOI:10.1109/ESSCIRC55480.2022.9911357

P. Crovetti, R. Rubino, P. Toledo, F. Musolino, H. Klimach, Yong Chen, A. Richelli

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引用次数: 1

摘要

本文提出了一种可重构、高阻抗、直流耦合的低频数字采集前端(DAFE)，适用于电源电压范围从0.2 ~ IV到600 pW。在轨道到轨道的输入范围内，匹配无关的直流精度是由新的超低面积时复用数字差分放大技术实现的，没有斩波和自动归零。该DAFE的180 nm测试芯片占地0.00945 mm2，在0.4 V电源下功耗为4.5 nW，增益带宽积为120 Hz，带内输入噪声为11.3µVrms，输入偏置电压标准差为137µV, CMRR为65.7dB, PSRR为63.8dB，在-12 dBFS下提供46.5dB-SFDR, 6.9位- enob数字化输出。

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A 0.01mm2, 0.4V-VDD, 4.5nW-Power DC-Coupled Digital Acquisition Front-End Based on Time-Multiplexed Digital Differential Amplification

A reconfigurable, high-impedance, DC-coupled low-frequency digital acquisition front-end (DAFE) suitable to operate under a power supply voltage ranging from 0.2 to IV down to 600 pW power is presented in this paper. Matching-indifferent DC accuracy over a rail-to-rail input range is uniquely achieved by the new time-multiplexed digital differential amplification technique at ultra-low area and without chopping and auto-zeroing. A 180 nm testchip of the proposed DAFE occupies 0.00945 mm2 and draws 4.5 nW at a 0.4 V supply, has a 120 Hz gain-bandwidth product, with an in-band input noise of 11.3 µVrms, a 137 µV input offset voltage standard deviation, 65.7dB CMRR, 63.8dB PSRR, and provides a 46.5dB-SFDR, 6.9 bit-ENOB digitized output at -12 dBFS.

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ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC)

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