MEMS post-processing of MPW dies using BSOI carrier wafers

Multi-project-wafer (MPW) services provide an economical route for prototyping of new electronic circuit designs. However, addition of MEMS functionality to MPW circuits by post-processing (also known as MEMS-last processing) is difficult and inefficient because MPW typically yields individual dies. One solution to this problem is to embed the MPW dies in a carrier wafer prior to MEMS processing. We have developed a process which allows 300 μm-thick CMOS dies to be embedded in a BSOI (bonded silicon-on-insulator) carrier prior to low-temperature processing for integration of metal MEMS. Deep reactive ion etching (DRIE) with an STS Multiplex ICP etcher is used to form cavities in the device layer of a BSOI wafer. By adjusting the passivation and etching cycles, the DRIE process has been optimized to produce near-vertical sidewalls when stopping on the buried oxide layer. The cavity sizes are closely matched to the die dimensions to ensure placement of the dies to within ±15 μm. Dies are placed in all the cavities, and then a photoresist layer is deposited by spin-coating and patterned to provide access to the required IC contact pads. The photoresist has the dual role of securing the dies and also planarizing the top surface of the carrier. After an appropriate baking cycle this layer provides a suitable base for multi-level electroplating or other low-temperature MEMS processing.