A. Hussain, H. Fahad, Nirpendra Singh, G. T. Torres Sevilla, U. Schwingenschlogl, M. Hussain
{"title":"用于提高硅CMOS性能的锡(Sn)","authors":"A. Hussain, H. Fahad, Nirpendra Singh, G. T. Torres Sevilla, U. Schwingenschlogl, M. Hussain","doi":"10.1109/NMDC.2013.6707470","DOIUrl":null,"url":null,"abstract":"We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon.","PeriodicalId":112068,"journal":{"name":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","volume":"124 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Tin (Sn) for enhancing performance in silicon CMOS\",\"authors\":\"A. Hussain, H. Fahad, Nirpendra Singh, G. T. Torres Sevilla, U. Schwingenschlogl, M. Hussain\",\"doi\":\"10.1109/NMDC.2013.6707470\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon.\",\"PeriodicalId\":112068,\"journal\":{\"name\":\"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)\",\"volume\":\"124 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NMDC.2013.6707470\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE 8th Nanotechnology Materials and Devices Conference (NMDC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NMDC.2013.6707470","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Tin (Sn) for enhancing performance in silicon CMOS
We study a group IV element: tin (Sn) by integrating it into silicon lattice, to enhance the performance of silicon CMOS. We have evaluated the electrical properties of the SiSn lattice by performing simulations using First-principle studies, followed by experimental device fabrication and characterization. We fabricated high-κ/metal gate based Metal-Oxide-Semiconductor capacitors (MOSCAPs) using SiSn as channel material to study the impact of Sn integration into silicon.