{"title":"一种基于亚阈值源耦合逻辑的超低功耗时域比较器","authors":"Samaneh Babayan-Mashhadi, Sajjad Mortazavi","doi":"10.1109/IRANIANCEE.2017.7985497","DOIUrl":null,"url":null,"abstract":"This paper presents a novel approach for designing ultra-low power, low-voltage time-domain comparators using source-coupled logic (SCL) topology, operating in weak-inversion (subthreshold) regime (STSCL). The proposed time-domain comparator (TDC) is simulated in 0.18µm CMOS technology. Simulation results reveal that at low supply voltage of 0.5V, the comparator consumes only 0.8µW operating at 1.1MHz, with the accuracy of approximately 1mV.","PeriodicalId":161929,"journal":{"name":"2017 Iranian Conference on Electrical Engineering (ICEE)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-05-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A novel ultra-low-power time-domain comparator based on subthreshold source-coupled logic\",\"authors\":\"Samaneh Babayan-Mashhadi, Sajjad Mortazavi\",\"doi\":\"10.1109/IRANIANCEE.2017.7985497\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a novel approach for designing ultra-low power, low-voltage time-domain comparators using source-coupled logic (SCL) topology, operating in weak-inversion (subthreshold) regime (STSCL). The proposed time-domain comparator (TDC) is simulated in 0.18µm CMOS technology. Simulation results reveal that at low supply voltage of 0.5V, the comparator consumes only 0.8µW operating at 1.1MHz, with the accuracy of approximately 1mV.\",\"PeriodicalId\":161929,\"journal\":{\"name\":\"2017 Iranian Conference on Electrical Engineering (ICEE)\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-05-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 Iranian Conference on Electrical Engineering (ICEE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IRANIANCEE.2017.7985497\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 Iranian Conference on Electrical Engineering (ICEE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IRANIANCEE.2017.7985497","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A novel ultra-low-power time-domain comparator based on subthreshold source-coupled logic
This paper presents a novel approach for designing ultra-low power, low-voltage time-domain comparators using source-coupled logic (SCL) topology, operating in weak-inversion (subthreshold) regime (STSCL). The proposed time-domain comparator (TDC) is simulated in 0.18µm CMOS technology. Simulation results reveal that at low supply voltage of 0.5V, the comparator consumes only 0.8µW operating at 1.1MHz, with the accuracy of approximately 1mV.
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