A CMOS microprocessor for telecommunications applications

THIS REPORT will cover an 8-bit microprocessorX fabricated with a silicon-gate CMOS technology and packaged in a 40-pin DIP. It embodies several architectural innovations and an extended instruction set affording exceptional computing power. Although the fabrication technology is CMOS, it was found that the use of non-complementary structures for certain portions of the logic resulted in a device with the functional density of NMOS, but with power dissipation and internal noise margins approaching that of CMOS. It was recognized early in the development program that an important measure of the computing power of a microprocessor is its efficiency in accessing memory. Accordingly, emphasis was placed on the efficient use of memory. A 16-bit address arithmetic unit (AAU) was provided on-chip to allow address calculations to take place in parallel with data manipulations. To further enhance the computing power, it was decided that the area limitation on the number of user registers which could be implemented on-chip should be avoided by placing all user registers in external RAM, as illustrated in Figure 1. One register set consists of 1 6 16-bit registers. Each register can be used as a 16-bit memory addressing register, a 16-bit accumulator, or an 8-bit accumulator. The source and destination operands of dyadic instructions are pointed to within the register set by an 8-bit DS pointer supplied. as the second byte of the instruction. The DS pointer contains a 4-bit D nibble identifying the destination operand within the register set and a 4-bit S nibble identifying the source operand. The location of the current rcgister set in external RAM is identified by a 16-bit register pointer (RP) maintained on-chip. Since the register pointer is under software control, the location of the register set in external RAM can be changcd on the fly. This makes it possible to form a stack of register sets in RAM, thus saving the current program arguments when executing single or nested subroutine calls. A special instruction allows the programmer to overlap successive rcgister sets by 4,8, or 12 words, thus effecting automatic sharing of 4, 8, or 1 2 arguments between a calling routine and its subroutine. To make efficient use of the large number of user registers available in the external register space, the instruction set provides eight addressing modes for each dyadic instruction and four addressing modes for each monadic instruction. In addition, a novel extension of the instruction set allows up to four distinct sub-modes within each addressing mode, bringing the total number of useablc dyadic modes to 21. Counting the various modes and sub-modes, the processor executes more than 400 unique instructions, some of which require up to 21 successive machine states to complete. Notable among these is a branchon-bit instruction which allows conditional branching on any