FLOVA的可测试性设计

Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434) Pub Date : 2000-08-28 DOI:10.1109/APASIC.2000.896972

Daehan Youn, Ohyoung Song, Hoon Chang

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摘要

本文介绍了基于VLIW架构的4级流水线操作的浮点数字信号处理器FLOVA的可测试性设计。全扫描设计、BIST (Built-In-Self-Test)和IEEE 1149.1边界扫描分别应用于触发器、浮点处理单元/嵌入式存储单元和I/O单元。

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Design-for-testability of the FLOVA

This paper describes design-for-testability of the floating point digital signal processor, called FLOVA, which is based on VLIW architecture with 4 stage pipeline operation. Full-scan design, BIST (Built-In-Self-Test), and IEEE 1149.1 boundary-scan are applied to the flip-flops, the floating point processing units/the embedded memory units, and the I/O cells, respectively.

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Proceedings of Second IEEE Asia Pacific Conference on ASICs. AP-ASIC 2000 (Cat. No.00EX434)

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