{"title":"Nd:YAG激光形成标准CMOS双能级金属化连接和断开的研究","authors":"H.-D. Hartmann, T. Hillmann-Ruge","doi":"10.1109/ICWSI.1990.63913","DOIUrl":null,"url":null,"abstract":"Nd:YAG laser processing of vertical links and cutting of interconnections in both metallization levels have been investigated. Main emphasis was on examination of the statistics of laser processing and the reliability of the processed antifuses. For this purpose, a special test chip has been designed and fabricated in a standard double level CMOS process. Laser cutting of interconnections is possible with one pulse in both metallization levels without passivation opening. For laser linking with the pulsed Nd:YAG, simply expanded interconnections turned out to be best suitable. Structures which are passivated prior to laser processing showed a significantly higher yield than depassivated combined with improved reproducibility of laser processing. Best yield of 99.4% with contact resistances <0.3 Omega has been achieved with expansions of 20*20 mu m/sup 2/. However, expansions of 14*14 mu m/sup 2/ are the best choice as yield is only slightly below that of the larger structures and consumption of area is much less. Accelerated life time tests with current densities up to 1*10/sup 6/ A/cm/sup 2/ and temperatures up to 270 degrees C were carried out. Materials were analysed with EDX, AES, and SIMS.<<ETX>>","PeriodicalId":206140,"journal":{"name":"1990 Proceedings. International Conference on Wafer Scale Integration","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1990-01-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Investigations of Nd:YAG laser formed connections and disconnections of standard CMOS double level metallizations\",\"authors\":\"H.-D. Hartmann, T. Hillmann-Ruge\",\"doi\":\"10.1109/ICWSI.1990.63913\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Nd:YAG laser processing of vertical links and cutting of interconnections in both metallization levels have been investigated. Main emphasis was on examination of the statistics of laser processing and the reliability of the processed antifuses. For this purpose, a special test chip has been designed and fabricated in a standard double level CMOS process. Laser cutting of interconnections is possible with one pulse in both metallization levels without passivation opening. For laser linking with the pulsed Nd:YAG, simply expanded interconnections turned out to be best suitable. Structures which are passivated prior to laser processing showed a significantly higher yield than depassivated combined with improved reproducibility of laser processing. Best yield of 99.4% with contact resistances <0.3 Omega has been achieved with expansions of 20*20 mu m/sup 2/. However, expansions of 14*14 mu m/sup 2/ are the best choice as yield is only slightly below that of the larger structures and consumption of area is much less. Accelerated life time tests with current densities up to 1*10/sup 6/ A/cm/sup 2/ and temperatures up to 270 degrees C were carried out. Materials were analysed with EDX, AES, and SIMS.<<ETX>>\",\"PeriodicalId\":206140,\"journal\":{\"name\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1990-01-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1990 Proceedings. International Conference on Wafer Scale Integration\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICWSI.1990.63913\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1990 Proceedings. International Conference on Wafer Scale Integration","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICWSI.1990.63913","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Investigations of Nd:YAG laser formed connections and disconnections of standard CMOS double level metallizations
Nd:YAG laser processing of vertical links and cutting of interconnections in both metallization levels have been investigated. Main emphasis was on examination of the statistics of laser processing and the reliability of the processed antifuses. For this purpose, a special test chip has been designed and fabricated in a standard double level CMOS process. Laser cutting of interconnections is possible with one pulse in both metallization levels without passivation opening. For laser linking with the pulsed Nd:YAG, simply expanded interconnections turned out to be best suitable. Structures which are passivated prior to laser processing showed a significantly higher yield than depassivated combined with improved reproducibility of laser processing. Best yield of 99.4% with contact resistances <0.3 Omega has been achieved with expansions of 20*20 mu m/sup 2/. However, expansions of 14*14 mu m/sup 2/ are the best choice as yield is only slightly below that of the larger structures and consumption of area is much less. Accelerated life time tests with current densities up to 1*10/sup 6/ A/cm/sup 2/ and temperatures up to 270 degrees C were carried out. Materials were analysed with EDX, AES, and SIMS.<>