四象限模拟乘法器的设计

IEEE International Symposium on Communications and Information Technology, 2004. ISCIT 2004. Pub Date : 2004-10-26 DOI:10.1109/ISCIT.2004.1412443

K. Dejhan, P. Prommee, W. Tiamvorratat, S. Mitatha, I. Chaisayun

{"title":"四象限模拟乘法器的设计","authors":"K. Dejhan, P. Prommee, W. Tiamvorratat, S. Mitatha, I. Chaisayun","doi":"10.1109/ISCIT.2004.1412443","DOIUrl":null,"url":null,"abstract":"The paper proposes a new four-quadrant analog multiplier which consists of a multiplier cell, a mixed signal circuit and three signal subtraction circuits. Its advantages are: the design has single ended inputs; the geometry of all the transistors is equal; its output can be the product of two signal voltage, or the product of a signal current and a signal voltage. Simulation results are demonstrated by PSpice to confirm the operation of the circuit.","PeriodicalId":237047,"journal":{"name":"IEEE International Symposium on Communications and Information Technology, 2004. ISCIT 2004.","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"A design of four-quadrant analog multiplier\",\"authors\":\"K. Dejhan, P. Prommee, W. Tiamvorratat, S. Mitatha, I. Chaisayun\",\"doi\":\"10.1109/ISCIT.2004.1412443\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper proposes a new four-quadrant analog multiplier which consists of a multiplier cell, a mixed signal circuit and three signal subtraction circuits. Its advantages are: the design has single ended inputs; the geometry of all the transistors is equal; its output can be the product of two signal voltage, or the product of a signal current and a signal voltage. Simulation results are demonstrated by PSpice to confirm the operation of the circuit.\",\"PeriodicalId\":237047,\"journal\":{\"name\":\"IEEE International Symposium on Communications and Information Technology, 2004. ISCIT 2004.\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-10-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Symposium on Communications and Information Technology, 2004. ISCIT 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISCIT.2004.1412443\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Communications and Information Technology, 2004. ISCIT 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISCIT.2004.1412443","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

提出了一种新的四象限模拟乘法器，它由一个乘法器单元、一个混合信号电路和三个信号减法电路组成。其优点是:设计为单端输入;所有晶体管的几何形状都是相同的;它的输出可以是两个信号电压的乘积，也可以是一个信号电流和一个信号电压的乘积。通过PSpice对仿真结果进行了验证，验证了电路的有效性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

A design of four-quadrant analog multiplier

The paper proposes a new four-quadrant analog multiplier which consists of a multiplier cell, a mixed signal circuit and three signal subtraction circuits. Its advantages are: the design has single ended inputs; the geometry of all the transistors is equal; its output can be the product of two signal voltage, or the product of a signal current and a signal voltage. Simulation results are demonstrated by PSpice to confirm the operation of the circuit.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE International Symposium on Communications and Information Technology, 2004. ISCIT 2004.

自引率

0.00%

发文量