Software aided failure analysis using ATPG tool

Automatic test pattern generation (ATPG) is recommended in order to obtain high test coverage quickly. For failure analysis, some standard ATPG tools offer in addition a feature to perform fault diagnosis on full scan designs. Software fault localization techniques become increasingly important in future designs, since in highly complex VHDL programmed designs, a standard analysis using functional test vectors is expendable and time consuming. This paper describes all steps necessary for project set-up and a flow for fault diagnosis. In order to minimize the list of possible failures (given by the tool) and to determine the physical location of the defect (x,y,z), a failure localization flow is presented. Initial results on ICs with both failures purposely induced by focused ion beam and real production failures represents an excellent starting point for further fault localization.