晶体管技术对单片3D集成电路节能的影响

2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA) Pub Date : 2016-04-25 DOI:10.1109/VLSI-TSA.2016.7480523

S. Samal, D. Nayak, M. Ichihashi, S. Banna, S. Lim

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引用次数: 0

摘要

在本文中，我们讨论了晶体管技术对单片3D集成电路比传统2D集成电路节能的影响。我们的研究结果是基于门级3D IC划分和全RTL到GDSII设计和分析低密度奇偶校验(LDPC)基准电路块，使用两种不同的硅验证铸造技术。这两种技术具有相同的标称工作电压，但在器件性能、功率和栅极电容方面有所不同。我们的研究结果表明，与高功率器件技术相比，单片3D IC在更低的器件功率和输入电容下为该技术提供了37.5%的节能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Impact of transistor technology on power savings in monolithic 3D ICs

In this paper, we discuss the impact of transistor technology on the power savings in monolithic 3D ICs over traditional 2D ICs. Our results are based on gate-level 3D IC partitioning and full RTL to GDSII design and analysis of a Low Density Parity Check (LDPC) benchmark circuit block with use of two different silicon validated foundry technologies. These two technologies have the same nominal operating voltage, but differ in terms of device performance, power, and gate capacitance. Our results show that monolithic 3D IC provides 37.5% more power savings for the technology with lower device power and input capacitance compared to that of a high power device technology.

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2016 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

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