M. Khazhinsky, K. Domanski, Guido Quax, Scott Ruth, F. Farbiz, N. Trivedi, H. Gossner
{"title":"识别锁定风险的EDA方法","authors":"M. Khazhinsky, K. Domanski, Guido Quax, Scott Ruth, F. Farbiz, N. Trivedi, H. Gossner","doi":"10.1109/EOSESD.2016.7592552","DOIUrl":null,"url":null,"abstract":"In this paper we review latchup protection verification methods and EDA challenges. We demonstrate complex static and transient latchup scenarios requiring advanced connectivity analysis. Using various EDA verification flows and tools we study latchup problems associated with grounded n-wells, biased n-wells and parasitic thyristors formed during ESD events.","PeriodicalId":239756,"journal":{"name":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"EDA approaches in identifying latchup risks\",\"authors\":\"M. Khazhinsky, K. Domanski, Guido Quax, Scott Ruth, F. Farbiz, N. Trivedi, H. Gossner\",\"doi\":\"10.1109/EOSESD.2016.7592552\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we review latchup protection verification methods and EDA challenges. We demonstrate complex static and transient latchup scenarios requiring advanced connectivity analysis. Using various EDA verification flows and tools we study latchup problems associated with grounded n-wells, biased n-wells and parasitic thyristors formed during ESD events.\",\"PeriodicalId\":239756,\"journal\":{\"name\":\"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"volume\":\"33 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EOSESD.2016.7592552\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 38th Electrical Overstress/Electrostatic Discharge Symposium (EOS/ESD)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EOSESD.2016.7592552","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper we review latchup protection verification methods and EDA challenges. We demonstrate complex static and transient latchup scenarios requiring advanced connectivity analysis. Using various EDA verification flows and tools we study latchup problems associated with grounded n-wells, biased n-wells and parasitic thyristors formed during ESD events.