Optimization of integrated dickson voltage-multipliers for RF energy harvesting

This paper presents the performance optimization of a UHF Dickson voltage-multiplier used for Radio-Frequency Energy Harvesting in 130 nm CMOS technology. The main axis of intervention is the strong reduction of parasitic capacitance with layout modifications. An improvement of existing pads is proposed in order to reduce the capacitive coupling. A novel Schottky diode is proposed as well. The latter is characterized by low area occupation and low parasitic capacitance without compromising forward current capabilities. A complete electrical characterization of the new device is included. Time and cost constraints prevented major manufacturing modifications (ex. technology node, circuit topology) yet a remarkable gain in performance is demonstrated. On-wafer measures of a 3-cells Dickson voltage-multiplier RF/DC efficiency will highlight the improvements.