用于异步σ - δ调制器中心频率增量的积分器箝位

T. Matić, T. Svedek, D. Vinko
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引用次数: 0

摘要

滞后比较器(施密特触发器)是异步σ - δ调制器(ASDM)的基本组成部分。如果迟滞比较器的传播延迟不等于零并且具有可测量值,则会影响ASDM输出频谱。由于ASDM是一个积分器和滞后比较器串行连接的电路,然后是一个负反馈回路,比较器的传播延迟会在ASDM输出信号触发事件中引入时序误差。因此,ASDM中心频率将低于在传播延迟等于零的情况下。本研究提供了滞回比较器传播延迟对ASDM输出频谱影响的数学分析。提出了利用积分器箝位电压提高ASDM中心频率的方法。数学分析、仿真和测量结果表明,中心频率部分增加。由于ASDM电路可以用作零输入信号的振荡器,因此中心频率可以得到显著改善。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Integrator clamping for asynchronous sigma-delta modulator central frequency increment
Hysteretic comparator (Schmitt trigger) is the basic part of the asynchronous sigma-delta modulator (ASDM). If propagation delay of a hysteretic comparator is not equal to zero and it has measurable value, than it affects the ASDM output frequency spectrum. As ASDM is a circuit with serial connection of an integrator and a hysteretic comparator followed by a negative feedback loop, propagation delay of the comparator will introduce the timing errors in ASDM output signal-triggering events. Therefore ASDM central frequency will be lower then it is in the case for propagation delay equal to zero. This study provides mathematical analysis of the hysteretic comparator propagation delay influence to the ASDM output frequency spectrum. The method for ASDM central frequency improvement using integrator voltage clamping has been proposed. Mathematical analysis, together with simulation and measurement results, shows partial central frequency increment. As ASDM circuit can be used as an oscillator for zero-input signals, central frequency improvement can be significant.
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