Pentium/sup R/ III微处理器封装设计与性能评估

IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565) Pub Date : 2001-10-29 DOI:10.1109/EPEP.2001.967666

A. Sarangi, G. Ji, T. Arabi, G. Taylor

{"title":"Pentium/sup R/ III微处理器封装设计与性能评估","authors":"A. Sarangi, G. Ji, T. Arabi, G. Taylor","doi":"10.1109/EPEP.2001.967666","DOIUrl":null,"url":null,"abstract":"This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.","PeriodicalId":174339,"journal":{"name":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-10-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Design and performance evaluation of Pentium/sup R/ III microprocessor packaging\",\"authors\":\"A. Sarangi, G. Ji, T. Arabi, G. Taylor\",\"doi\":\"10.1109/EPEP.2001.967666\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.\",\"PeriodicalId\":174339,\"journal\":{\"name\":\"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-10-29\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEP.2001.967666\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.2001.967666","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 8

摘要

本文描述了一种设计方法，以确定所需的芯片电容器的数量及其放置方案，为最新的Pentium/sup R/ III微处理器封装基板的最佳性能。讨论了电容器对电源的影响及其性能和放置方案，并与测量结果进行了比较。概述了性能改进，并比较了目前的0.13 /spl mu/m和以前的0.18 /spl mu/m硅封装技术，该技术旨在与现有系统兼容。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design and performance evaluation of Pentium/sup R/ III microprocessor packaging

This paper describes a design methodology to determine the number of chip capacitors needed and its placement scheme for the latest Pentium/sup R/ III microprocessor package substrate for optimum performance. The effect of capacitors on the power supply and its performance and placement schemes are discussed and compared against measurements. Performance improvements are outlined and compared between the current 0.13 /spl mu/m and the previous 0.18 /spl mu/m silicon package technology designed for compatibility with existing systems.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

IEEE 10th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No. 01TH8565)

自引率

0.00%

发文量