{"title":"InP MISFET的制造与性能","authors":"T. Kawakami, M. Okamura","doi":"10.1109/IEDM.1980.189862","DOIUrl":null,"url":null,"abstract":"N-channel normally-off InP MISFETs for high-gain and high-speed application have been developed, using the following fabrication techniques: (1)Sulphur diffusion process into p- and semi-insulating InP wafers for low resistive source and drain of the n-channel FET. (2)Al2O3CVD method onto the InP substrate. (3)n-channel formation on the semi-insulating InP substrate surface. (4)A pseudo self-alignment technique for eliminating gate-drain and gate-source parasitic capacitances. Conductance and drift properties have been studied together with MIS diode capacitance measurement and AES analysis.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"2010 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Fabrication and performance of InP MISFET\",\"authors\":\"T. Kawakami, M. Okamura\",\"doi\":\"10.1109/IEDM.1980.189862\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"N-channel normally-off InP MISFETs for high-gain and high-speed application have been developed, using the following fabrication techniques: (1)Sulphur diffusion process into p- and semi-insulating InP wafers for low resistive source and drain of the n-channel FET. (2)Al2O3CVD method onto the InP substrate. (3)n-channel formation on the semi-insulating InP substrate surface. (4)A pseudo self-alignment technique for eliminating gate-drain and gate-source parasitic capacitances. Conductance and drift properties have been studied together with MIS diode capacitance measurement and AES analysis.\",\"PeriodicalId\":180541,\"journal\":{\"name\":\"1980 International Electron Devices Meeting\",\"volume\":\"2010 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1980.189862\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1980.189862","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
N-channel normally-off InP MISFETs for high-gain and high-speed application have been developed, using the following fabrication techniques: (1)Sulphur diffusion process into p- and semi-insulating InP wafers for low resistive source and drain of the n-channel FET. (2)Al2O3CVD method onto the InP substrate. (3)n-channel formation on the semi-insulating InP substrate surface. (4)A pseudo self-alignment technique for eliminating gate-drain and gate-source parasitic capacitances. Conductance and drift properties have been studied together with MIS diode capacitance measurement and AES analysis.
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