K. Tsuchida, Y. Ogwaki, M. Ohta, D. Takashima, S. Watanabe
{"title":"稳定参考线(SRL)技术用于规模化dram","authors":"K. Tsuchida, Y. Ogwaki, M. Ohta, D. Takashima, S. Watanabe","doi":"10.1109/VLSIC.1989.1037508","DOIUrl":null,"url":null,"abstract":"The stabilized reference-line (SRL) technique, which reduces bit-line interference noise, is described. This technique can eliminate the capacitance coupling noise generated when the cell data are transferred to the bit line. As a result, the noise generated by the sensing timing difference, which is caused by the coupling noise, does not arise. Furthermore, the SRL technique can be realized by modifying the conventional folded bit-line architecture. Therefore, it is easy to apply the SRL technique to high-density DRAMs. >","PeriodicalId":136228,"journal":{"name":"Symposium 1989 on VLSI Circuits","volume":"79 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-05-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"10","resultStr":"{\"title\":\"The stabilized reference-line (SRL) technique for scaled DRAMs\",\"authors\":\"K. Tsuchida, Y. Ogwaki, M. Ohta, D. Takashima, S. Watanabe\",\"doi\":\"10.1109/VLSIC.1989.1037508\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The stabilized reference-line (SRL) technique, which reduces bit-line interference noise, is described. This technique can eliminate the capacitance coupling noise generated when the cell data are transferred to the bit line. As a result, the noise generated by the sensing timing difference, which is caused by the coupling noise, does not arise. Furthermore, the SRL technique can be realized by modifying the conventional folded bit-line architecture. Therefore, it is easy to apply the SRL technique to high-density DRAMs. >\",\"PeriodicalId\":136228,\"journal\":{\"name\":\"Symposium 1989 on VLSI Circuits\",\"volume\":\"79 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-05-25\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"10\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Symposium 1989 on VLSI Circuits\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIC.1989.1037508\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Symposium 1989 on VLSI Circuits","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIC.1989.1037508","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The stabilized reference-line (SRL) technique for scaled DRAMs
The stabilized reference-line (SRL) technique, which reduces bit-line interference noise, is described. This technique can eliminate the capacitance coupling noise generated when the cell data are transferred to the bit line. As a result, the noise generated by the sensing timing difference, which is caused by the coupling noise, does not arise. Furthermore, the SRL technique can be realized by modifying the conventional folded bit-line architecture. Therefore, it is easy to apply the SRL technique to high-density DRAMs. >