Analysis of leakage currents in multiple gate poly-si thin film transistors for active matrix liquid crystal displays

In this paper we show good agreement between numerical simulations and experimental data of the electrical characteristics of multiple gate poly-crystalline silicon (poly-Si) thin film transistors (TFTs). We focus on leakage current, as this is the most critical TFT characteristic for pixel switches in high resolution active matrix liquid crystal displays (AMLCD). The minimum leakage current ( Imin) determines grey level performance, while the sharpness of the minimum determines the range of negative gate bias required to maintain leakages close to I m i n , Leakage currents in poly-Si TFTs have been shown to be caused by a high electric field tunneling mechanism at specific traps, probably associated with intra-grain defects [l]. Various strategies are currently being employed to reduce leakage currents, but multiple gate devices [2] are preferential on account of their ease of implementation. In multiple gate structures the gated regions are connected by heavily doped channel regions. Experimentally we show [3] that while NMOS multiple gate structures reduce I m i n , they do not reduce the slope of the leakage current increase with larger reverse gate biases, V, , . This result is contrary to initial expectations that multiple gate TFTs would reduce the slope of the reverse V, , leakage, as the drain bias (Vds) is divided between the gated regions, and as minority carriers generated in the drain high field region would recombine in the (or one of the) heavily doped channel region(s) without reaching the source. In this paper we demonstrate, for the first time, why multiple gate TFTs have the same leakage increase a t negative gate voltages as single gate TFTs. Leakage currents are simulated by adding a single tunneling trap with a temperature independent tunneling mechanism to an effective medium model [l]. With increasing reverse V, , the maximum channel electric field moves from the edge of the gated region (second) near the TFT drain to the drain edge of the gated region nearest to the source (first), causing the leakage current slope to be independent of the number of gates. Multiple gate structures lower Imin as the vds is divided between the different gated regions, reducing the peak channel electric field. The leakage of a double gate TFT a t Vds = 10 Volts is higher than that of a single gate device a t vds=Sv. The experimental data of the dependence of leakage on reverse V,, are in good agreement with the simulation results. Contour plots of the channel electric field for vds= 1OV in a double gate TFT show that for VgS above the value needed for minimum leakage current (Vgsmin) the highest field is near to the edge of the gated region nearest the device drain. Carrier concentration profiles show that few minority carriers generated in the high field region flow through the central heavily doped region to the source. For V, , more negative than Vgsmin the point of highest electric field moves to the drain edge of the gated region nearest to the source, Once the gated region nearest the drain becomes sufficiently conductive, the largest potential drop within the TFT is a t the drain end of the source gated region. Now minority carriers generated by a tunneling mechanism in this first gated region flow to the source, increasing the leakage current. This causes double gate TFTs to have the same slope reverse gate bias characteristics as single gate TFTs. TFTs with progressively higher number of gates also have the same leakage slope as a single gate device as the point of highest channel electric field always moves to the drain edge of the gated region nearest to the source.