突发模式:128位分组密码的新加速模式

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012786

Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa

{"title":"突发模式:128位分组密码的新加速模式","authors":"Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa","doi":"10.1109/CICC.2002.1012786","DOIUrl":null,"url":null,"abstract":"\"Burst mode\" is a new cipher mode, which is devised dedicatedly for the high performance implementation of Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, the burst mode achieves a considerable increase in the throughput by employing a novel stream cipher mechanism which can encrypt 64 plaintext blocks through 16 invocations of the block cipher encryption operation. This paper investigates the hardware/software (HW/SW) codesign of the burst mode, to be implemented as an accelerator core running in parallel with a software-based block cipher. Implementation results show that the burst mode with the use of this hardware accelerator raises the speed of the software implementation of AES by four times, achieving the maximum rate of 1.3 Gbps.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"229 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Burst mode: a new acceleration mode for 128-bit block ciphers\",\"authors\":\"Y. Mitsuyama, Z. Andales, T. Onoye, I. Shirakawa\",\"doi\":\"10.1109/CICC.2002.1012786\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\\\"Burst mode\\\" is a new cipher mode, which is devised dedicatedly for the high performance implementation of Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, the burst mode achieves a considerable increase in the throughput by employing a novel stream cipher mechanism which can encrypt 64 plaintext blocks through 16 invocations of the block cipher encryption operation. This paper investigates the hardware/software (HW/SW) codesign of the burst mode, to be implemented as an accelerator core running in parallel with a software-based block cipher. Implementation results show that the burst mode with the use of this hardware accelerator raises the speed of the software implementation of AES by four times, achieving the maximum rate of 1.3 Gbps.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"229 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012786\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012786","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 3

摘要

“突发模式”是专为高性能实现高级加密标准(AES)和其他下一代128位分组密码算法而设计的一种新型密码模式。与传统模式相比，突发模式采用了一种新颖的流密码机制，通过16次分组密码加密操作可以加密64个明文块，从而大大提高了吞吐量。本文研究了突发模式的硬件/软件协同设计，实现了一个加速器核心与一个基于软件的分组密码并行运行。实现结果表明，使用该硬件加速器的突发模式将AES的软件实现速度提高了4倍，达到了1.3 Gbps的最高速率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Burst mode: a new acceleration mode for 128-bit block ciphers

"Burst mode" is a new cipher mode, which is devised dedicatedly for the high performance implementation of Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, the burst mode achieves a considerable increase in the throughput by employing a novel stream cipher mechanism which can encrypt 64 plaintext blocks through 16 invocations of the block cipher encryption operation. This paper investigates the hardware/software (HW/SW) codesign of the burst mode, to be implemented as an accelerator core running in parallel with a software-based block cipher. Implementation results show that the burst mode with the use of this hardware accelerator raises the speed of the software implementation of AES by four times, achieving the maximum rate of 1.3 Gbps.

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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