基于adc的接收机设计:挑战与机遇

2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS) Pub Date : 2017-10-01 DOI:10.1109/CSICS.2017.8240461

A. Sheikholeslami

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引用次数: 1

摘要

本文回顾了一组使数据速率超过10Gb/s的架构和电路技术，并探讨了我们向更高数据速率移动时的一系列设计挑战和考虑因素。我们特别回顾了基于ADC的设计及其挑战和权衡，包括ADC分辨率、过采样率和功耗。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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ADC-based receiver designs: Challenges and opportunities

This paper reviews a set of architecture and circuit techniques that have enabled data rates beyond 10Gb/s, and explores a range of design challenges and considerations as we move to higher data rates. In particular, we review ADC-based designs and their challenges and tradeoffs, including ADC resolution, oversampling ratio, and power consumption.

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来源期刊

2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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