Data manipulator network for WSI designs

Multiprocessor system architectures require the use of INterconnection NETworks (INNETs) to provide for movement of data or instructions between memory and the processing elements. When an INNET is an integral part of the system, a WSI implementation will generally require a large fraction of the wafer area. This paper presents an area-reducing algorithm for the data manipulator network in silicon implementations where two or more levels of metal are available. The objective of multilevel metalization, i.e., more than the traditional two-level metalization, is two-fold: (a) to reduce the silicon area used by the wiring, and (b) to provide for mask programmability of metal layers. The emphasis of this paper is on the first of these aspects.<>