基于vhdl的数字电路合成:一个案例研究

F.L. Viana, F. Damiani
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引用次数: 0

摘要

目前,超大规模集成电路的计算机辅助设计要求在足够高的抽象水平上指定设计。这种方法允许设计人员根据一组相互作用的组件来描述系统,这有助于在复杂设计中重用子系统并缩短设计周期。本文介绍了数字电路设计中描述与综合方法的一个案例研究。不同的数字加法算法在VHDL中编码,并在两种不同的商业电子设计自动化(EDA)环境中自动合成。对所得到的电路进行了仿真,并对总体结果进行了展示和讨论。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
VHDL-based digital circuit synthesis: a case study
Present day computer-aided design of VLSI circuits calls for specifying the design at a sufficiently high level of abstraction. This approach allows the designers to describe systems in terms of a set of interacting components, which facilitates the reuse of subsystems in a complex design and reduces the design cycle. This paper describes a case study of the Description-and-Synthesis methodology for digital circuit design. Distinct digital addition algorithms were coded in VHDL and automatically synthesized using two different commercial Electronic Design Automation (EDA) environments. The resulting circuits were simulated and the overall results are shown and discussed.
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