{"title":"模拟电路的低成本直流BIST:一个案例研究","authors":"P. Petrashin, C. Dualibe, W. Lancioni, L. Toledo","doi":"10.1109/LATW.2013.6562668","DOIUrl":null,"url":null,"abstract":"This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity-to-faults node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm low-voltage transconductor, showing good fault coverage for both catastrophic and parametric faults.","PeriodicalId":186736,"journal":{"name":"2013 14th Latin American Test Workshop - LATW","volume":"684 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Low-cost DC BIST for analog circuits: A case study\",\"authors\":\"P. Petrashin, C. Dualibe, W. Lancioni, L. Toledo\",\"doi\":\"10.1109/LATW.2013.6562668\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity-to-faults node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm low-voltage transconductor, showing good fault coverage for both catastrophic and parametric faults.\",\"PeriodicalId\":186736,\"journal\":{\"name\":\"2013 14th Latin American Test Workshop - LATW\",\"volume\":\"684 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2013-04-03\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2013 14th Latin American Test Workshop - LATW\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/LATW.2013.6562668\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 14th Latin American Test Workshop - LATW","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/LATW.2013.6562668","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low-cost DC BIST for analog circuits: A case study
This paper presents a DC analog testing technique based on a simple voltage comparison of the highest sensitivity-to-faults node, which is found by simulation. The technique is a structural, fault driven testing approach and can be applied to any analog circuit with very few extra added circuitry. A proof of concept has been implemented in a 65nm low-voltage transconductor, showing good fault coverage for both catastrophic and parametric faults.
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