基于多次采样的数字开关电源系统时钟降频

2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia) Pub Date : 2015-06-01 DOI:10.1109/ICPE.2015.7168192

Y. Yau, K. Hwu, W. Jiang

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引用次数: 2

摘要

本文提出了基于单比较器采样的采样结构，可以将系统时钟频率从100MHz显著降低到25MHz，从而减小芯片面积。通过开关频率为200kHz的同步整流降压变换器对该方法进行了验证，数字控制器以Altera公司的EP1C3T100 FPGA为控制内核，采用VHDL语言对该控制器进行编程。

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System clock reduction based on multiple sampling for digital switching power supplies

In this paper, the proposed sampling structure based on one-comparator sampling is presented, which can significantly reduce the system clock frequency from 100MHz to 25MHz, so as to reduce chip area. This method is verified by a synchronously-rectified buck converter with a switching frequency of 200kHz, and the digital controller takes as a control kernel the EP1C3T100 FPGA created by Altera Co., along with the VHDL language to program this controller.

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来源期刊

2015 9th International Conference on Power Electronics and ECCE Asia (ICPE-ECCE Asia)

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