使用参数化子电路单元的rfic统一建模和设计方法

Dong-Hun Shin, C. Yue
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引用次数: 7

摘要

本文首次提出了一个基于单元的rfic建模和设计平台,旨在通过消除原理图和布局后仿真之间的迭代来缩短设计周期时间,并最大限度地降低昂贵的掩模重新旋转的风险。该方法基于预先表征的射频子电路单元库,其中不仅包含有源器件和无源器件,还包含路由互连,系统地缓解了由于实际电路和器件模型测试结构之间的布局差异而导致的常见射频模型不准确。通过利用子电路级RF电路的模块化,与使用预表征单晶体管的传统方法相比,所提出的设计平台实现了电路设计灵活性和器件模型精度之间的平衡。本文介绍了一个0.13 μ m CMOS RF子电路单元库的参数化子电路单元布局的实现和宏建模技术。给出了用于验证宏电路模型的表征测试芯片的测量结果
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A unified modeling and design methodology for RFICs using parameterized sub-circuit cells
This paper presents, for the first time, a cell-based modeling and design platform for RFICs aiming to shorten design cycle time by eliminating iterations between schematic and post-layout simulations and to minimize the risk for costly mask re-spin. Based on a pre-characterized RF sub-circuit cell library, which contains not only active devices and passive components but also routing interconnects, this methodology systematically alleviates the common RF model inaccuracy due to layout discrepancies between actual circuits and device model test structures. By exploiting the modularity in RF circuits at the sub-circuit level, the proposed design platform achieves a balance between circuit design flexibility and device model accuracy compared to the conventional approach of using pre-characterizing single transistors. This paper describes the implementation of the parameterized sub-circuit cell layout and the macro modeling techniques for a 0.13-mum CMOS RF sub-circuit cell library. Measurement results from a characterization test chip for validating the macro circuit models are presented
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