{"title":"基于低PPM缺陷故障模型的存储器有效测试","authors":"D. Lam, S. Y. Khim","doi":"10.1109/MT.1993.263142","DOIUrl":null,"url":null,"abstract":"The authors describe how an understanding of failure modes and models allows better test algorithms and patterns to be generated to screen out those type of failures without lowering the general yield. Much of this understanding comes about only after extensive electrical analysis. A few case studies experienced by the authors are presented.<<ETX>>","PeriodicalId":248811,"journal":{"name":"Records of the 1993 IEEE International Workshop on Memory Testing","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-08-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Effective tests for memories based on faults models for low PPM defects\",\"authors\":\"D. Lam, S. Y. Khim\",\"doi\":\"10.1109/MT.1993.263142\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The authors describe how an understanding of failure modes and models allows better test algorithms and patterns to be generated to screen out those type of failures without lowering the general yield. Much of this understanding comes about only after extensive electrical analysis. A few case studies experienced by the authors are presented.<<ETX>>\",\"PeriodicalId\":248811,\"journal\":{\"name\":\"Records of the 1993 IEEE International Workshop on Memory Testing\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-08-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Records of the 1993 IEEE International Workshop on Memory Testing\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MT.1993.263142\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Records of the 1993 IEEE International Workshop on Memory Testing","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MT.1993.263142","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effective tests for memories based on faults models for low PPM defects
The authors describe how an understanding of failure modes and models allows better test algorithms and patterns to be generated to screen out those type of failures without lowering the general yield. Much of this understanding comes about only after extensive electrical analysis. A few case studies experienced by the authors are presented.<>