先进CMOS可靠性挑战

Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test Pub Date : 2014-04-28 DOI:10.1109/VLSI-DAT.2014.6834931

C. Prasad

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引用次数: 9

摘要

本文从可靠性的角度回顾了先进CMOS工艺节点的晶体管，并涵盖了一些重要的挑战和解决方案。研究了65nm至22nm节点的各种模式的物理机制，重点研究了HK/MG和三栅极/FinFET等破坏性变化。还强调了建模非理想性和变化的重要性，并与现有研究进行了比较，对20nm以下的缩放进行了预测。

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Advanced CMOS reliability challenges

This work reviews transistors of advanced CMOS process nodes from a reliability perspective and covers some of the important challenges and solutions. Physical mechanisms for various modes are investigated for 65nm to 22nm nodes with focus on disruptive changes such as HK/MG and Tri-gate/FinFET. The importance of modeling non-idealities and variation is also emphasized, and projections are made for scaling to sub-20nm with comparisons to existing research.

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Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test

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