{"title":"DANNA:用于非结构化稀疏的维度感知神经网络加速器","authors":"Xinyu Liu, Haigang Feng","doi":"10.1109/CISCE58541.2023.10142599","DOIUrl":null,"url":null,"abstract":"With the development of technology in deep neural network (DNN) pruning, Neural Acceleration Processor can be designed to get more efficiency advantage by exploiting all sparsity in neural network. However, sparse data has irregular coordination, which result that the exist sparse designs have serious storage waste and high latency. In this work, we present a Dimension-Aware Neural Network Acceleration (DANNA) to optimize those problems. Specifically, DANNA employs novel Dimension-first dataflow and custom microarchitecture, which substantially reduce both memory amounts and memory access collision (hash collision). Furthermore, DANNA leverages a fixed channel-share-LUT based on channel reuse characteristics in convolution to replace the traditional tedious coordinator comparison, which saves consumption of logic.","PeriodicalId":145263,"journal":{"name":"2023 5th International Conference on Communications, Information System and Computer Engineering (CISCE)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-04-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"DANNA: A Dimension-Aware Neural Network Accelerator for Unstructured Sparsity\",\"authors\":\"Xinyu Liu, Haigang Feng\",\"doi\":\"10.1109/CISCE58541.2023.10142599\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"With the development of technology in deep neural network (DNN) pruning, Neural Acceleration Processor can be designed to get more efficiency advantage by exploiting all sparsity in neural network. However, sparse data has irregular coordination, which result that the exist sparse designs have serious storage waste and high latency. In this work, we present a Dimension-Aware Neural Network Acceleration (DANNA) to optimize those problems. Specifically, DANNA employs novel Dimension-first dataflow and custom microarchitecture, which substantially reduce both memory amounts and memory access collision (hash collision). Furthermore, DANNA leverages a fixed channel-share-LUT based on channel reuse characteristics in convolution to replace the traditional tedious coordinator comparison, which saves consumption of logic.\",\"PeriodicalId\":145263,\"journal\":{\"name\":\"2023 5th International Conference on Communications, Information System and Computer Engineering (CISCE)\",\"volume\":\"108 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2023-04-14\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2023 5th International Conference on Communications, Information System and Computer Engineering (CISCE)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CISCE58541.2023.10142599\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 5th International Conference on Communications, Information System and Computer Engineering (CISCE)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CISCE58541.2023.10142599","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
DANNA: A Dimension-Aware Neural Network Accelerator for Unstructured Sparsity
With the development of technology in deep neural network (DNN) pruning, Neural Acceleration Processor can be designed to get more efficiency advantage by exploiting all sparsity in neural network. However, sparse data has irregular coordination, which result that the exist sparse designs have serious storage waste and high latency. In this work, we present a Dimension-Aware Neural Network Acceleration (DANNA) to optimize those problems. Specifically, DANNA employs novel Dimension-first dataflow and custom microarchitecture, which substantially reduce both memory amounts and memory access collision (hash collision). Furthermore, DANNA leverages a fixed channel-share-LUT based on channel reuse characteristics in convolution to replace the traditional tedious coordinator comparison, which saves consumption of logic.