用于100Gb/200Gb 32nm CMOS相干光接收芯片的可编程有源时钟脊柱

Naim Ben-Hamida, C. Kurowski, R. Gibbins, J. Weng, Ted Wong, John Lindsay, H. Mah, S. Aouini, Andrew McCarthy
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引用次数: 0

摘要

介绍了一种100G/200G相干光接收机的有源时钟分配网络。该芯片拥有超过10亿个晶体管,采用32纳米CMOS体技术,具有11个金属层。有源时钟脊实现了低倾斜、低抖动和低功耗时钟分布解决方案。此外,调试友好的时钟环境提供了易于观察、测试和重新配置的特性;因此,能够快速进入市场。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Programmable Active Clock Spine for 100Gb/200Gb Coherent Optical Receiver Chip in 32nm CMOS
This paper describes an active clock distribution network for a 100G/200G coherent optical receiver. The chip has more than 1 billion transistors implemented in 32nm CMOS bulk technology with 11 metal layers. The active clock spines enabled a low-skew, low jitter, and low power clock distribution solution. In addition, a debug-friendly clocking environment provides easy observability, testing, and reconfiguration features; hence, enabling rapid time to market.
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