Naim Ben-Hamida, C. Kurowski, R. Gibbins, J. Weng, Ted Wong, John Lindsay, H. Mah, S. Aouini, Andrew McCarthy
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Programmable Active Clock Spine for 100Gb/200Gb Coherent Optical Receiver Chip in 32nm CMOS
This paper describes an active clock distribution network for a 100G/200G coherent optical receiver. The chip has more than 1 billion transistors implemented in 32nm CMOS bulk technology with 11 metal layers. The active clock spines enabled a low-skew, low jitter, and low power clock distribution solution. In addition, a debug-friendly clocking environment provides easy observability, testing, and reconfiguration features; hence, enabling rapid time to market.
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