AC stress reliability study of a new high voltage transistor for logic memory circuits

This paper presents a junction reliability study on a new architecture of high voltage transistor with a double poly gate for Non-Volatile Memory (NVM) Technology. The experiments results are supported by TCAD simulations. The drain-bulk AC stress was performed on the new architecture and compared with the conventional demonstrating an important improvement in terms of reliability, for different bias conditions, taking advantage of its design architecture. Finally, process and design optimizations of the new architecture are presented.