An All Digital CMOS Serial Link Transceiver with 3x Over-sampling Based Data Recovery

An all digital CMOS serial link transceiver with 3x over-sampling based data recovery circuit is presented in this paper. The modified data recovery circuit is simpler than those using 3x over-sampling recovery circuit in (Chih-Kong Ken Yang et al., 1998) and (Chih-Kong Ken Yang and Horowitz). An all digital DLL (delay locked loop) is used to generate the multiphase clocks and a new CPRD (coarse phase-difference range decision) unit is introduced here to reduce the lock time. The whole design's feasibility is verified by the Verilog HDL modeling. And the DLL's performance is simulated by HSPICE in SMIC 0.18mum CMOS technology. The simulation results show that the system is workable. The data recovery's latency of the transceiver is reduced to 5 cycles and the whole system can hold about 1Gbps data bit rate in the worst case