375V部分SOI SJ LDNMOS北斗系统限制的三维仿真研究

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD) Pub Date : 2023-05-28 DOI:10.1109/ISPSD57135.2023.10147409

Elizabeth Kho Ching Tee, M. Antoniou, D. Green, A. Hölke, F. Udrea

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引用次数: 0

摘要

本文研究了将部分绝缘体上硅的SJ LDNMOS的击穿电压(BDS)能力提高到460V的新技术。这是基于两种不同概念和技术的独特组合，即部分绝缘体上硅(PSOI)和超结(SJ)，以实现高效的功率集成电路平台。采用基于“区域分解”三维TCAD仿真的新颖三维设计，降低了器件BDS对手柄晶圆二极管电压的灵敏度。在复杂的端接区内，由于静电电位线向器件区域中点方向发生了90°的面外弯曲而产生的热点位置被成功识别并消除。

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3D simulation study of 375V partial SOI SJ LDNMOS BDS limitation

This paper investigates novel techniques of extending the breakdown voltage (BDS) capability of the partial silicon-on-insulator SJ LDNMOS up to 460V. This is based on a unique combination of two different concepts and technologies, namely the Partial Silicon-On-Insulator (PSOI) and Superjunction (SJ) to achieve a highly effective platform for Power Integrated Circuit. The device BDS sensitivity to the handle wafer diode voltage is mitigated by using a novel 3D design based on “domain decomposition” 3D TCAD simulations. The hot spot location in the complex termination area, which is due to out-of-plane (90°) bending of electrostatic potential lines towards the midpoint of the device area, is successfully identified and eliminated.

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来源期刊

2023 35th International Symposium on Power Semiconductor Devices and ICs (ISPSD)

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