Design of Power Efficient Fault Tolerant Registers using Modified Hybrid Protection Technique

This paper proposes modified Hybrid Protection techniques to design fault tolerant registers using combination of Triple Modular Redundancy (TMR), Single Error Correcting (SEC) codes and Double Error Detecting (DED) codes, which are necessary to be implemented because of the modern-day soft errors that occur due to radiation. Using these techniques, the circuit area, consumption of power and timing are main constraints, when applied on Application Specific Integrated Circuits (ASIC) which is mainly dependent on design requirements. This paper brings in the idea of modified Hybrid Technique-I which introduces a combination of TMR on higher activity bits of a register and SEC-SEC on lower activity bits, and modified Hybrid Technique-II where TMR is applied on higher activity bits and SEC-DED on lower activity bits based on the threshold, set for division of register with respect to activity factor. This leads to the achievement of increase in number of bits which can be corrected in any register with 24.5% and 64.7% decrease in power overhead in modified Hybrid technique I and II respectively as compared to existing hybrid protection technique.