基于设计层次的可达性优化混合尺寸布局

Yi-Lin Chuang, Gi-Joon Nam, C. Alpert, Yao-Wen Chang, Jarrod A. Roy, Natarajan Viswanathan
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引用次数: 30

摘要

可达性是现代大规模混合尺寸电路布局的强制性指标,通常需要处理数百个大型宏和数百万个小型标准单元。然而,大多数现有的学术混合大小放置器要么只关注最小的无线长度,要么不考虑可移动宏对路由的影响。为了弥补这些不足,本文将设计层次信息作为分析放置框架中的一种新的围栏力。与最先进的可达性驱动的放矿器在放置过程中简单地移除网边界框不同,本文利用两种不同的优化力,即全局围栏力和局部扩展力,来确定标准单元和宏的位置。我们利用设计层次信息来确定全局块分布,并在局部通过网络拓扑估计增加额外的扩展力以保持块之间足够的自由空间。通过这两种力之间的相互作用,我们的放置器可以很好地平衡可达性和无线性。实验结果表明,该算法在所有已发表的算法中具有最佳的路由可达性和路由时间。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Design-hierarchy aware mixed-size placement for routability optimization
Routability is a mandatory metric for modern large-scale mixed-size circuit placement which typically needs to handle hundreds of large macros and millions of small standard cells. However, most existing academic mixed-size placers either focus on wirelength minimization alone, or do not consider the impact of movable macros on routing. To remedy these insufficiencies, this paper formulates design-hierarchy information as a novel fence force in an analytical placement framework. Unlike a state-of-the-art routability-driven placer that simply removes net bounding boxes during placement, this paper utilizes two different optimization forces, the global fence force and the local spreading force, to determine the positions of both standard cells and macros. We utilize design-hierarchy information to determine block distributions globally, and locally we add additional spreading forces to preserve sufficient free space among blocks by a net-topology estimation. With the interactions between these two forces, our placer can well balance routability and wirelength. Experimental results show that our placer can achieve the best routability and routing time among all published works.
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