用于ii相ATLAS-MDT TDC的130 nm CMOS锁相环

Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018) Pub Date : 2019-05-24 DOI:10.22323/1.343.0092

A. Pipino, M. Matteis, F. Resta, A. Baschirotto, H. Kroha, R. Richter, O. Kortner, J. Zhu, J. Wang

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引用次数: 2

摘要

特点:•无触发和触发模式•边缘和对模式•可编程输出线速率:80(传统)，320,640 Mbps•重新设计台积电130nm技术-时钟和相位发生器(ePLL)•4时钟相位时间插补器@320MHz; 3125 ns/4 = 0,78ns LSB - TDC时间数字化单元(x24)和数字处理逻辑触发和读出方案二期MDT系统

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A 130 nm CMOS PLL for Phase-II ATLAS-MDT TDC

Global Project: Development of a TDC for ATLAS MDT Phase-II Upgrade Features: • Trigger-less and trigger mode • Edge and pair modes • Programmable output lines rates: 80 (legacy), 320, 640 Mbps • Re-design in TSMC 130nm technology – Clock and phase generator (ePLL) • 4 clock phase time interpolator @320MHz  3,125 ns/4 = 0,78ns LSB – TDC time-digitization unit (x24) and digital processing logics Trigger and readout scheme for the Phase-II MDT system

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Proceedings of Topical Workshop on Electronics for Particle Physics — PoS(TWEPP2018)

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